1. Field of the Invention
This invention relates to a charge coupled device, in particular, to a charge coupled device such as a CCD delay line for producing signals by using a fundamental clock signal.
2. Description of the Prior Art
Recent CCD delay lines include therein many peripheral circuits from a viewpoint of easiness of use. Especially, in the case of a video signal processing, etc., about 5 MHz is required as the signal band. Accordingly, a frequency of 2 to 6 fsc (color subcarrier frequency) is used as the drive frequency for CCD delay lines.
In order to provide a clock frequency of 2 to 6 fsc, it is necessary to use a PLL (Phase-Locked Loop) circuit. Accordingly, an employment of other ICs results in an increased cost and an increased number of parts of the entirety. In view of this, CCD delay line including a PLL circuit on the same chip are being developed.
In a CCD delay line including therein a PLL circuit, a clock having a frequency of fsc is supplied to the PLL circuit as an external clock signal in order to activate the delay line. However, this signal of fsc component may leak into other circuits inside the CCD delay line. Thus, a bad influence may occur by that false signal. For example, in the case where there has been leakage of a signal of fsc component when a monochromatic picture should be monitored, the signal of fsc component is superimposed on an original signal. As a result, such a signal component is judged to be a color component on a monitor, and a color is produced on the monochromatic picture.